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12:2, differential-to-lvds multiplexer ICS854S202I-01 idt ? / ics ? lvds multiplexer 1 ics854s202ayi-01 rev. a january 8, 2007 preliminary g eneral d escription the ICS854S202I-01 is a 12:2 differential-to- lvds clock multiplexer which can operate up to 700mhz and is a member of the hiperclocks? family of high performance clock solutions from idt. the ICS854S202I-01 has 12 selectable dif- ferential clock inputs, any of which can be independently routed to either of the two lvds outputs. the clkx, nclkx input pairs can accept lvpecl, lvds, cml or sstl levels. the fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. hiperclocks? ic s b lock d iagram f eatures two differential 2.5v lvds clock outputs twelve selectable differential clock inputs clkx, nclkx pairs can accept the following differential input levels: lvpecl, lvds, hstl, sstl, hcsl maximum output frequency: >3ghz propagation delay: 650ps (typical) input skew: tbd output skew: 25ps (typical) part-to-part skew: tbd additive phase jitter, rms (12khz ? 20mhz): 0.16ps (typical) full 2.5v operating supply mode -40c to 85c ambient operating temperature available in both standard (rohs 5) and lead-free (rohs 6) packages 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 ICS854S202I-01 48-pin lqfp 7mm x 7mm x 1.4mm package body y package top view clk2 nclk2 sela_0 sela_1 v dd qa nqa gnd sela_2 sela_3 clk3 nclk3 clk9 nclk9 selb_0 selb_1 v dd qb nqb gnd selb_2 selb_3 clk8 nclk8 nclk10 clk10 gnd nclk11 clk11 oeb v dd clk0 nclk0 gnd clk1 nclk1 nclk4 clk4 gnd nclk5 clk5 v dd oea clk6 nclk6 gnd clk7 nclk7 qa nqa oea qb nqb oeb pulldown pulldown 4 4 sela_[3:0] clk0 nclk0 selb_[3:0] clk1 nclk1 clk2 nclk2 clk3 nclk3 clk8 nclk8 clk9 nclk9 clk10 nclk10 clk11 nclk11 clk4 nclk4 clk5 nclk5 clk6 nclk6 clk7 nclk7 p in a ssignment the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? lvds multiplexer 2 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary t able 1. p in d escriptions ( continued on next pag e ) r e b m u ne m a ne p y tn o i t p i r c s e d 12 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 22 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / , 3 , 4 , 9 0 1 , 0 _ a l e s , 1 _ a l e s , 2 _ a l e s 3 _ a l e s t u p n in w o d l l u p t u p n i l o r t n o c e e s . s t u p t u o a k n a b r o f s n i p t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a t n o i t c n u f . b 3 e l b a t e e s 3 4 , 2 3 , 5v d d r e w o p. s n i p y l p p u s e v i t i s o p 7 , 6a q n , a qt u p t u o. s l e v e l e c a f r e t n i s d v l . s t u p t u o k c o l c 6 4 , 9 3 , 9 2 , 2 2 , 5 1 , 8d n gr e w o p. d n u o r g y l p p u s r e w o p 1 13 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 2 13 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 3 14 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 4 14 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 6 15 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 7 15 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 3 4 , 8 1v d d r e w o p. s n i p y l p p u s e v i t i s o p 9 1a e ot u p n ip u l l u p a q n / a q f o g n i l b a s i d d n a g n i l b a n e s l o r t n o c . n i p e l b a n e t u p t u o . s l e v e l e c a f n r e t n i l t t v l / s o m c v l . s t u p t u o 0 26 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 1 26 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 3 27 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 4 27 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 5 28 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 6 28 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n , 7 2 , 8 2 , 3 3 4 3 , 3 _ b l e s , 2 _ b l e s , 1 _ b l e s 0 _ b l e s t u p n in w o d l l u p t u p n i l o r t n o c e e s . s t u p t u o b k n a b r o f s n i p t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a t n o i t c n u f . c 3 e l b a t e e s 1 3 , 0 3b q , b q nt u p t u o. s l e v e l e c a f r e t n i s d v l . s t u p t u o k c o l c 5 39 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 6 39 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 7 30 1 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 8 30 1 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 0 41 1 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 1 41 1 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
idt ? / ics ? lvds multiplexer 3 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary r e b m u ne m a ne p y tn o i t p i r c s e d 2 4b e ot u p n ip u l l u p b q n / b q f o g n i l b a s i d d n a g n i l b a n e s l o r t n o c . n i p e l b a n e t u p t u o . a 3 e l b a t e e s . s l e v e l e c a f n r e t n i l t t v l / s o m c v l . s t u p t u o 4 40 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 5 40 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 7 41 k l ct u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 8 41 k l c nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a m s t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k ? r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k ? t able 3b. oea, oeb c ontrol i nput f unction t able t u p n it u p t u o b e o , a e ob q n / b q , a q n / a q 0) w o l c i g o l ( d e l b a s i d 1e v i t c a t able 1. p in d escriptions ( continued )
idt ? / ics ? lvds multiplexer 4 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary t able 3b. sel_a c ontrol i nput f unction t able t u p n i l o r t n o c a q n / a q o t d e t c e l e s t u p n i 3 _ a l e s2 _ a l e s1 _ a l e s0 _ a l e s 0000 0 k l c n , 0 k l c 000 1 1 k l c n , 1 k l c 00 10 2 k l c n , 2 k l c 00 11 3 k l c n , 3 k l c 0100 4 k l c n , 4 k l c 0101 5 k l c n , 5 k l c 0110 6 k l c n , 6 k l c 0 111 7 k l c n , 7 k l c 1000 8 k l c n , 8 k l c 10 0 1 9 k l c n , 9 k l c 10 10 0 1 k l c n , 0 1 k l c 10 1 1 1 1 k l c n , 1 1 k l c 1100 h / l 110 1 h / l 1110 h / l 1111 h / l t able 3c. sel_b c ontrol i nput f unction t able t u p n i l o r t n o c b q n / b q o t d e t c e l e s t u p n i 3 _ b l e s2 _ b l e s1 _ b l e s0 _ b l e s 0000 0 k l c n , 0 k l c 000 1 1 k l c n , 1 k l c 00 10 2 k l c n , 2 k l c 00 11 3 k l c n , 3 k l c 0100 4 k l c n , 4 k l c 0101 5 k l c n , 5 k l c 0110 6 k l c n , 6 k l c 0 111 7 k l c n , 7 k l c 1000 8 k l c n , 8 k l c 10 0 1 9 k l c n , 9 k l c 10 10 0 1 k l c n , 0 1 k l c 10 1 1 1 1 k l c n , 1 1 k l c 1100 h / l 110 1 h / l 1110 h / l 1111 h / l
idt ? / ics ? lvds multiplexer 5 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary t able 4b. lvcmos/lvttl dc c haracteristics , v dd = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 7 . 1v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -7 . 0v i h i t n e r r u c h g i h t u p n i , 3 : 0 _ a l e s 3 : 0 _ b l e s v d d v 5 2 6 . 2 =0 5 1a b e o , a e ov d d v 5 2 6 . 2 =5a i l i t n e r r u c w o l t u p n i , 3 : 0 _ a l e s 3 : 0 _ b l e s v d d v , v 5 2 6 . 2 = n i v 0 =5 -a b e o , a e ov d d v , v 5 2 6 . 2 = n i v 0 =0 5 1 -a t able 4c. d ifferential dc c haracteristics , v dd = 2.5v5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, i o (lvds) contin uous current 10ma surge current 15ma package thermal impedance, ja 67.2c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v dd = 2.5v5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s r e w o p 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 0 1 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 1 k l c : 0 k l c 1 1 k l c n : 0 k l c n v d d v = n i v 5 2 6 . 2 =0 5 1a i l i t n e r r u c w o l t u p n i 1 1 k l c : 0 k l cv d d v , v 5 2 6 . 2 = n i v 0 =5 -a 1 1 k l c n : 0 k l c nv d d v , v 5 2 6 . 2 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 ?v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i x k l c n , x k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n d d . v 3 . 0 +
idt ? / ics ? lvds multiplexer 6 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary t able 4d. lvds dc c haracteristics , v dd = 2.5v5%, t a = -40c to 85c t able 5. ac c haracteristics , v dd = 2.5v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 3 >z h g p t h l ; h g i h o t w o l , y a l e d n o i t a g a p o r p 1 e t o n 0 5 6s p p t l h ; w o l o t h g i h , y a l e d n o i t a g a p o r p 1 e t o n 0 5 6s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 5 2s p t ) i ( k s3 e t o n ; w e k s t u p n i d b ts p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p d b ts p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b , n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r 5 e t o n , z h m 2 5 . 5 5 1 : e g n a r n o i t a r g e t n i z h m 0 2 - z h k 2 1 6 1 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 1 1s p c d oe l c y c y t u d t u p t u o 0 5% x u m n o i t a l o s i n o i t a l o s i x u mf t u o z h g 2 . 1 <5 4b d . e s i w r e h t o d e t o n s s e l n u , z h m 0 0 5 t a d e r u s a e m s r e t e m a r a p l l a v m o r f d e r u s a e m : 1 e t o n d d v o t t u p n i e h t f o 2 / d d . t u p t u o e h t f o 2 / v t a d e r u s a e m . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n d n a s e g a t l o v y l p p u s e m a s e h t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 4 e t o n v t a d e r u s a e m s i t u p t u o e h t , e c i v e d h c a e n o t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d d . 2 / . k c o l c t u p n i e n o y l n o g n i v i r d : 5 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 0 0 4v m ? v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 3 . 1v ? v s o v s o e g n a h c e d u t i n g a m 0 5v m
idt ? / ics ? lvds multiplexer 7 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary a dditive p hase j itter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz as with most timing specifications, phase noise measurements have issues. the primary issue relates to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z additive phase jitter at 155.52mhz (12khz - 20mhz) = 0.16ps (typical)
idt ? / ics ? lvds multiplexer 8 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary p arameter m easurement i nformation d ifferential i nput l evel 2.5v o utput l oad ac t est c ircuit p art - to -p art s kew o utput s kew t sk(pp) qy qx part 1 part 2 t sk(o) nqy nqx qy qx nqy nqx v dd clk0:clk11 nclk0:nclk11 gnd v dd clock outputs 20% 80% 80% 20% t r t f v od o utput r ise /f all t ime t pd nclk0:nclk11 nqa, nqb p ropagation d elay clk0:clk11 qa, qb scope qx nqx lv d s 2.5v5% power supply +? float gnd v cmr cross points v pp
idt ? / ics ? lvds multiplexer 9 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary t pw t period t pw t period odc = x 100% nqa, nqb i nput s kew o utput d uty c ycle /p ulse w idth /p eriod nclk0: nclk11 nqa, nqb qa, qb t pd1 t pd2 tsk(i) = |t pd1 - t pd2 | clk0: clk11 qa, qb nclky nqa, nqb clky qa, qb o ffset v oltage s etup ? ? ? 100 out out lv d s dc input v od / v od v dd out out lvds dc input ? ? ? v os / v os v dd d ifferential o utput v oltage s etup
idt ? / ics ? lvds multiplexer 10 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary i nputs : clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds o utput all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v v_ref r1 1k c1 0.1u r2 1k single ended clock input clkx nclkx vdd
idt ? / ics ? lvds multiplexer 11 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary f igure 2c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 2d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the f igure 2a. h i p er c lock s clk/nclk i nput d riven by idt h i p er c lock s lvhstl d river vendor of the driver component to confirm the driver termina- tion requirements. for example in figure 2a, the input termination applies for idt hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 2e. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
idt ? / ics ? lvds multiplexer 12 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary f igure 3. t ypical lvds d river t ermination line environment. for buffer with multiple ldvs driver, it is rec- ommended to terminate the unused outputs. 2.5v lvds d river t ermination figure 3 shows a typical termination for lvds driver in character- istic impedance of 100 ? differential (50 ? single) transmission 2. 5v 100 ohm differential transmission line 2. 5v lvds_driv er r1 100 + - 100 ? ? ? ? ? differential transmission line
idt ? / ics ? lvds multiplexer 13 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS854S202I-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854S202I-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. ? power (core) max = v dd_max * i dd_max = 2.625v * 110ma = 288.75mw 2. junction temperature. junction temperature, tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 57.4c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.289w * 57.4c/w = 101.6c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 48-l ead lqfp, f orced c onvection ja vs. air flow (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 67.2c/w 57.4c/w 53.8c/w
idt ? / ics ? lvds multiplexer 14 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary r eliability i nformation t ransistor c ount the transistor count for ICS854S202I-01 is: 8,485 ja vs. air flow (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 67.2c/w 57.4c/w 53.8c/w t able 7. ja vs . a ir f low t able for 48 l ead lqfp
idt ? / ics ? lvds multiplexer 15 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary p ackage o utline - y s uffix for 48 l ead lqfp t able 8. p ackage d imensions n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s c b b m u m i n i ml a n i m o nm u m i x a m n 8 4 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 7 1 . 02 2 . 07 2 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 5 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 5 . 5 e c i s a b 0 5 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -8 0 . 0 reference document: jedec publication 95, ms-026
idt ? / ics ? lvds multiplexer 16 ics854s202ayi-01 rev. a january 8, 2007 ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - i y a 2 0 2 s 4 5 8 s c i1 0 i a 2 0 2 s 4 s c ip f q l d a e l 8 4y a r tc 5 8 o t c 0 4 - t 1 0 - i y a 2 0 2 s 4 5 8 s c i1 0 i a 2 0 2 s 4 s c ip f q l d a e l 8 4l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l 1 0 - i y a 2 0 2 s 4 5 8 s c id b tp f q l " e e r f - d a e l " d a e l 8 4y a r tc 5 8 o t c 0 4 - t f l 1 0 - i y a 2 0 2 s 4 5 8 s c id b tp f q l " e e r f - d a e l " d a e l 8 4l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2006 integrated device technology, inc. all rights reserved. product spe cifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ICS854S202I-01 12:2, differential-lvds mul tiplexer preliminary

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